The present invention relates to non-volatile flash memory (“NVM”) semiconductor device which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. More particularly, the invention relates to a NVM semiconductor device having two-bits per cell employed in a virtual ground (VG) array. Also, the invention relates to a method for programming the two-bits per cell NVM semiconductor in the VG array. This innovation provides for a more capable VG array due to the doubled memory density per cell, which is also known as multi-level flash memory. The invention also impacts an NVM semiconductor device “window of operation” that permits more effective use of two-bits per cell NVM semiconductor devices. The invention also addresses the leakage current issue experienced with VG arrays when some erasing, programming, and reading methods are applied.
Multi-level, or multi-bit, flash memory cells provide a solution for increasing the amount of data that can be stored on a memory device without consuming more space. Whereas a single-bit cell can store only two states, “on” and “off” (typically labeled “0” and “1”), a cell having n bits and using binary encoding is capable of storing up 2n states. Thus, a two-bit cell may store data in four discrete states, “00”, “01”, “10” and “11” which is distinctly more efficient that the “0” or “1” state alone. FIG. 1A shows a typical two-bit cell, generally labeled 10. The cell 10 has symmetrical source/drain regions 14 and 16 in connection with a semiconductor well 30. The well 30 and a gate 26 are separated from a charge trapping layer 20 by an oxide region 18. In this configuration, as seen in FIG. 1F, the left side of the charge trapping layer 20 is designated as the “left bit” or Bit-L 34, and the right side as the “right bit” or Bit-R 36.
A limitation with two-bits per cell NVM semiconductor devices is a narrow “window of operation” that exists after the conventional programming of a two-bit cell. The window of operation is generally described as the difference in the threshold voltage (Vt) of a programmed cell bit as compared to the Vt of the un-programmed (erased) state. FIG. 1G illustrates the distribution of the un-programmed Vt of the right bit 36 of FIG. 1H as well as the distribution of the programmed Vt of the right bit 36 of FIG. 1H. As FIG. 1G indicates, the window of operation of 4V in this example is that difference between the highest Vt of the un-programmed state 1 and the lowest Vt of the programmed state 0. As a cell bit is programmed from an un-programmed state (a logic 1) to a programmed state (a logic 0) the threshold voltage increases for that bit. Voltage thresholds and techniques for programming the left and right bits of NVM semiconductors are discussed in U.S. Pat. No. 6,011,725 (Eitan '725), the contents of which is incorporated by reference herein.
The greater the difference in the un-programmed Vt from the programmed Vt allows for a clearer distinction between the programmed and un-programmed cell states for one-bit cells or to describe the state of the right bit and/or the left bit for two-bit cells. A greater difference between Vt of the two bits in a two-bit cell also allows for a clearer discrimination among the four distinct programmed cell states referred to above. Greater differences between the programmed and un-programmed state Vt, in other words a larger operational window, can be accomplished by programming from a lower initial voltage threshold Vti. The lower the Vti, then the greater discrimination that will exist between the un-programmed state and the programmed state. Memory cells with a larger operation window have the advantage of tolerating more charge loss and read disturb and such cells have greater endurance, which refers to the cycling of the program and erase steps.
As indicated in FIG. 1G, the window of operation is also known as the second bit window of operation regarding a two-bit memory cell. The second bit window of operation is generally described as the effect on the Vt of one bit that is not undergoing a programming action by the programming of the other bit associated with the same cell (the target bit). In other words, as seen in FIGS. 2A and 2B, as the left bit is programmed from its initial state with Vti to its programmed state with a programmed Vt, the Vt of the right bit undergoes a “shift” in that although it is not being programmed, the right bit Vt is adjusted higher anyway and thus has a higher Vt for the same bit state that existed before the left bit was programmed. As FIGS. 3A and 3B indicate, the lower the initial Vt (Vti) of both the bit to be programmed (the target bit of the target cell) and the non-programmed bit (non-target bit of the target cell), then the lower Vt shift for the non-programmed bit will be induced as the programmed bit undergoes a larger Vt shift for programming purposes. As seen in FIG. 3A, the erasure method of the present invention provides an erased Vt that is lower than the Vti of the memory cell 10.
When subjected to a conventional erase, program, and read operation the non-targeted NVM cells of the VG array will experience leakage current flow. FIG. 2C illustrates the leakage current flow exhibited by NVM cells of a VG array that are not targeted during a conventional programming step of a target NVM cell or cells.
Programming (i.e. charge injection) in two-bit NVM cells is achieved by various conventional hot carrier injection methods such as channel hot electron injection (CHE), source side injection (SSI) or channel initiated secondary electron (CHISEL).
It is desirable to begin programming of two-bit memory cells in a VG array with a lower initial Vt (Vti) so that there will be a larger widow between the Vt of the programmed state and Vt of the non-programmed state in that there is a smaller Vt shift imposed on the non-programmed bit as the other, target bit, is programmed. It is also desirable to conduct an erase, program, and read operation on a VG array with two-bit NVM cells and limit the leakage current from non-targeted cells in the array.